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參數(shù)資料
| 型號： | DS33ZH11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100 |
| 文件頁數(shù)： | 50/169頁 |
| 文件大小： | 1049K |
| 代理商： | DS33ZH11 |
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DS33Z11 Ethernet Mapper
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8.15 BERT
The BERT can be used for generation and detection of BERT patterns. The BERT is a software programmable
test pattern generator and monitor capable of meeting most error performance requirements for digital
transmission equipment. The following restrictions are related to the BERT:
The RDEN and TDEN are inputs that can be used to “gap” bits.
BERT will transmit even when the device is set for X.86 mode and TDEN is configured as an output.
The normal traffic flow is halted while the BERT is in operation.
If the BERT is enabled for a Serial port, it will override the normal connection.
If there is a connection overridden by the BERT, when BERT operation is terminated the normal operation is
restored.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test
pattern payload for the programmable test pattern.
BERT Features
PRBS and QRSS patterns of 2
9
-1, 2
15
-1 2
23
-1 and QRSS pattern support
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable
(length n = 1 to 32 and pattern = 0 to (2
n
– 1)).
24-bit error count and 32-bit bit count registers
Programmable bit error insertion. Errors can be inserted individually
8.15.1 Receive Data Interface
8.15.1.1 Receive Pattern Detection
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x
n
+ x
y
+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback
is bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator
is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to one if
the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is
forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection
performs either PRBS synchronization or repetitive pattern synchronization.
8.15.1.2 PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
resynchronization is initiated. Automatic pattern resynchronization can be disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS33ZH11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10/100 ENETXPORT HMODE MAP IND RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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| DS3404FP000/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,404,3P480V,JG63,SC |
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