參數(shù)資料
型號(hào)： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁(yè)數(shù)： 22/169頁(yè)
文件大?。?/td> 1049K
代理商： DS33ZH11
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DS33Z11 Ethernet Mapper
22 of 169
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
D6
C5
—
IOZ
Data Bit 6:
Bidirectional data bit 6 of the microprocessor
interface. Not driven when
CS
= 1 or
RST
= 0.
D7
C6
—
IOZ
Data Bit 7:
Bidirectional data bit 7 of the microprocessor
interface. Most Significant Bit.
CS
= 1 or
RST
= 0.
SPI_CS
B8
B5
O
Active-Low SPI Chip Select:
Provides the chip select to
the external EEPROM, when the SPI port is in master
mode.
SPI Clock Phase:
MISO is sampled on the falling edge
when CKPHA is set high, and on the rising edge when set
low.
MOSI is updated on the rising edge when CKPHA is set
high, and on the falling edge when set low.
CKPHA
F6
—
I
CS
C1
—
I
Active-Low Chip Select:
This pin must be taken low for
read/write operations. When
CS
is high, the
RD/DS
and
WR
signals are ignored.
RD/DS
E1
—
I
Active-Low Read-Data Strobe (Intel Mode):
The
DS33Z11 drives the data bus (D0-D7) with the contents of
the addressed register while
RD
and
CS
are both low.
Active-Low Data Strobe (Motorola Mode):
Used to latch
data through the microprocessor interface.
DS
must be low
during read and write operations.
Active-Low Write (Intel Mode):
The DS33Z11 captures
the contents of the data bus (D0-D7) on the rising edge of
WR
and writes them to the addressed register location.
CS
must be held low during write operations.
Read Write (Motorola Mode):
Used to indicate read or
write operation. R
W
must be set high for a register read
cycle and low for a register write cycle.
Active-Low Interrupt Output:
Outputs a logic zero when
an unmasked interrupt event is detected.
INT
is
deasserted when all interrupts have been acknowledged
and serviced. Inactive state is programmable in register
GL.CR1.
Active-Low Reset:
An active low signal on this pin resets
the internal registers and logic. This pin should remain low
until power, SYSCLKI, RX_CLK, and TX_CLK are stable,
then set high for normal operation. This input requires a
clean edge with a rise time of 25ns or less to properly
reset the device.
WR
/R
W
E2
—
I
INT
F3
—
OZ
RST
D8
C1
I
HWMODE
D5
A3
I
Hardware Mode:
Connect to V
DD
to place the device in
Hardware Mode. MODEC[1:0] determines the default
hardware setting to be used. This pin must be held low for
control by a microprocessor or an external EEPROM.
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