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參數(shù)資料
| 型號： | DS33ZH11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100 |
| 文件頁數(shù)： | 40/169頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | DS33ZH11 |
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DS33Z11 Ethernet Mapper
40 of 169
8.12 Flow Control
Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z11
allows for optional flow control based on the queue high watermark or through host processor intervention. There
are 2 basic mechanisms that are used for flow control:
In half duplex mode, a jam sequence is sent that causes collisions at the far end. The collisions cause the
transmitting node to reduce the rate of transmission.
In full duplex mode, flow control is initiated by the receiving node sending a pause frame. The pause
frame has a timer parameter that determines the pause timeout to be used by the transmitting node.
Note that the terms “transmit queue” and “receive queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
The following flow control options are possible:
Automatic flow control can be enabled in hardware mode by the AFCS and FULLDS pins
Automatic flow control can be enabled in software mode with the SU.GCR.ATFLOW bit. Note that the user
does not have control over SU.MACFCR.FCE and FCB bits if ATFLOW is set. The mechanism of sending
pause or jam is dependent only on the receive queue high threshold.
Manual flow control can be performed through software when SU.GCR.ATFLOW = 0. The host processor
must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR.FCE bits.
Note that in order to use flow control, the receive queue size (in AR.RQSC1) must be 02h or greater. The receive
queue high threshold (in SU.RQHT) must be set to 01h or greater, but must be less than the queue size. If the
high threshold is set to the same value as the queue size, automatic flow control will not be effective. The high
threshold must always be set to less than the corresponding queue size.
The following table provides all the options on flow control mechanism for DS33Z11.
Table 8-4 Options for Flow Control
HARDWARE MODE
Half duplex,
Flow control
With respect
to SU.RQHT
1
1
0
N/A
SOFTWARE MODE
Configuration
No flow
control
Full duplex,
Flow control
With respect
to SU.RQHT
1
1
1
N/A
Half Duplex;
Manual Flow
Control
Half Duplex;
Automatic
Flow Control
Full Duplex;
Manual Flow
Control
Full Duplex;
Automatic
Flow Control
HWMODE Pin
AFCS Pin
FULLDS Pin
ATFLOW Bit
JAME Bit
1
0
0
0
0
0
0
N/A
0
0
N/A
0
1
N/A
1
0
N/A
1
1
N/A
N/A
N/A
N/A
Controlled By
User
Controlled
Automatically
N/A
N/A
FCB Bit
(Pause)
N/A
N/A
Controlled
Automatically
N/A
N/A
Controlled by
User
Controlled
Automatically
FCE Bit
N/A
Set to AFCS
pin = Low
Set to AFCS
pin = High
Controlled By
User
Controlled
Automatically
Controlled By
User
Controlled
Automatically
Pause Timer
N/A
N/A
Set to 140h
N/A
N/A
Programmed
by User
Programmed
by User
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