
DS33Z11 Ethernet Mapper
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Table 8-9 Specific Functional Default Values for Hardware Mode
Functional Block
Register Reference
Default Value in
Hardware Mode
Description
Global
Connection between Serial and
Ethernet Interfaces
GL.CON1
0000 0001b
Connection established for Serial 1 to Ethernet 1.
Serial Data
Transmit Serial Interface
Configuration
LI.TSLCR
0000 0000b
Transmit Data enable is not supported and should be
tied high. The user must provide gapped clocks to
mask bits if needed. The Transmit Serial data will
output on the rising edge of TCLKI1-4.
Serial Interface Reset and
Power-down
LI.RSTPD
0000 0000b
In default hardware mode the Serial Interface
Transmitter is powered up and ready to go.
Transmit FCS
LI.TPPCL
0001 0000b*
FCS is set to 16 bits for the HDLC Transmitter.
Transmit Inter Frame Gap
LI.TIFGC
0000 0001b
Transmit inter frame gap is one byte. The value is 7E.
Receive FCS
LI.RPPCL
0001 0000b*
Receive HDLC FCS is set to 16 bits. Receive
scrambling and bit ordering controlled by hardware pins
Receive Maximum Packet
Length
LI.RMPSC
2016 bytes
The receive maximum packet length is set to 2016
bytes not including the HDLC FCS.
Any packets greater than 2016 bytes are rejected.
Receive Serial Port
Configuration
LI.RSLCR
0000 0000b
Receive RDEN enable will not be supported and should
be tied high. The Received data is sampled on the
falling edge and gapped clock is supported.
Transmit packet Resend
Criteria
SU.TFRC
0000 0000b
Any error: Jabber timeout, Loss of carrier, Excessive
deferral, Late collision, Excessive collisions, Under run,
collision, deferred, heartbeat fail will result in resending
of packets
Receive Packet Rejection
Control
SU.RFRC
0000 0000b
Broadcast frames, Control frames, and Errored packets
are rejected.
Receiver Maximum Size
SU.RMFSR
0111 1110b
The maximum receiver packet size is 2016 bytes
including the MAC FCS. Any packet larger that 2016 is
rejected
Ethernet
MAC Control Register
SU.MACCR
0000 0000
0000 0100
0000 0000
0000 1100b*
Duplex mode(bit 20) is determined by the FULLDS pin
(MSB to LSB)
MAC Flow Control Register
SU.MACFCR
0000 0001
0100 0000
0000 0000
0000 0000b*
Flow control is determined by the AFCS pin.
Pause Timer = 320 (140h) Slots
(MSB to LSB)