參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 123/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
123 of 169
9.6.2 MAC Registers
The control Registers related to the control of the individual Mac’s are shown in the following table. The DS33Z11
keeps statistics for the packet traffic sent and received. The register address map is shown in the following table.
Note that the addresses listed are the indirect addresses that must be provided to SU.MACRADH/SU.MACRADL
or SU.MACAWH/SU.MACAWL.
Register Name:
Register Description:
Register Address:
0000h:
Bit #
Name
Default
0001h:
Bit #
Name
Default
0002h:
Bit #
Name
Default
0003h:
Bit #
Name
Default
Bit 28: Heartbeat Disable (HDB)
When set to 1, the heartbeat (SQE) function is disabled. This bit should be set
to 1 when operating in MII mode.
Bit 27: Port Select (PS)
This bit should be equal to 0 for proper operation.
Bit 23: Disable Receive Own (DRO)
When set to 1, the MAC disables the reception of frames while TX_EN is
asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared
when operating in full-duplex mode.
Bit 21: Loopback Operating Mode (OMLO)
When set to 1, data is looped from the transmit side, back to the
receive side, without being transmitted to the PHY.
Bit 20: Full-Duplex Mode Select (F)
When set to 1, the MAC transmits and receives data simultaneously. When
in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.
SU.MACCR
MAC Control Register
0000h (indirect)
31
30
29
28
HDB
0
27
PS
0
26
25
24
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
23
DRO
0
22
21
20
F
0
19
18
17
16
Reserved
0
OML0
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
15
14
13
12
LCC
0
11
10
09
08
Reserved
0
Reserved
0
Reserved
0
Reserved
0
DRTY
0
Reserved
0
ASTP
0
07
06
05
DC
0
04
03
TE
0
02
RE
0
01
00
BOLMT1
0
BOLMT0
0
Reserved
0
Reserved
0
Reserved
0
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