參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 77/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
77 of 169
Register Name:
Register Description:
Register Address:
GL.TRQIE
Global Transmit Receive Queue Interrupt Enable
0Ah
5
4
-
TQ1IE
0
0
Bit #
Name
Default
7
-
0
6
-
0
3
-
0
2
-
0
1
-
0
0
RQ1IE
0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE)
Setting this bit to 1 enables an interrupt on TQ1IS.
Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE)
Setting this bit to 1 enables an interrupt on RQ1IS.
Register Name:
GL.TRQIS
Register Description:
Global Transmit Receive Queue Interrupt Status
Register Address:
0Bh
Bit #
7
6
5
Name
-
-
-
Default
0
0
0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IS)
If this bit is set to 1, the Transmit Queue 1 has interrupt
status event. Transmit queue events are transmit queue-crossing thresholds and queue overflows.
Bit 0: Receive Queue 1 Interrupt Status (RQ1IS)
If this bit is set to 1, the Receive Queue 1 has interrupt status
event. Receive queue events are transmit queue-crossing thresholds and queue overflows.
4
3
-
0
2
-
0
1
-
0
0
TQ1IS
0
RQ1IS
0
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: BERT Interrupt Enable (BIE)
Setting this bit to 1 enables an interrupt on BIS.
GL.BIE
Global BERT Interrupt Enable
0Ch
5
-
0
7
-
0
6
-
0
4
-
0
3
-
0
2
-
0
1
-
0
0
BIE
0
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