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參數(shù)資料
| 型號(hào)： | DS33ZH11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100 |
| 文件頁(yè)數(shù)： | 33/169頁(yè) |
| 文件大?。?/td> | 1049K |
| 代理商： | DS33ZH11 |
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DS33Z11 Ethernet Mapper
33 of 169
8.3.1 Serial Interface Clock Modes
The Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLKI and
RCLKI) are inputs, and can be gapped.
8.3.2 Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation. The
user has the option of using the internally generated REF_CLKO output to simplify the system design.
Table 8-1
outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is generated by
division of the 100 MHz system clock input by the user on SYSCLKI. The frequency of the REF_CLKO pin is
automatically determined by the DS33Z11 based on the state of the RMIIMIIS pin. The REF_CLKO output can be
used as a REF_CLK for the Ethernet Interface by connecting REF_CLKO to REF_CLK. The REF_CLKO function
can be turned off with the GL.CR1.RFOO bit.
In RMII mode, receive and transmit timing is always synchronous to a 50 MHz clock input on the REF_CLK pin.
The source of REF_CLK is expected to be the external PHY. The user has the option of using the 50MHz
REF_CLKO output as the timing source for the PHY. More information on RMII mode can be found in
Section
8.14.2
.
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to
be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and
RX_CLK) are output by the DS33Z11, and are derived from the 25 MHz REF_CLK input. Any 25 MHz reference
may be used, but the user may choose to use the REF_CLKO output to avoid adding another system clock. More
information on MII mode can be found in Section
8.14.1
.
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