參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 100/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive FCS Errored Packet Latched (REPL)
This bit is set when a packet with an errored FCS is
detected.
100 of 169
LI.RPPSRL
Receive Packet Processor Status Register Latched
105h
7
6
5
4
3
2
1
0
REPL
-
RAPL
-
RIPDL
-
RSPDL
-
RLPDL
-
REPCL
-
RAPCL
-
RSPCL
-
Bit 6: Receive Aborted Packet Latched (RAPL)
This bit is set when a packet with an abort indication is detected.
Bit 5: Receive Invalid Packet Detected Latched (RIPDL)
This bit is set when a packet with a non-integer
number of bytes is detected.
Bit 4: Receive Small Packet Detected Latched (RSPDL)
This bit is set when a packet smaller than the minimum
packet size is detected.
Bit 3: Receive Large Packet Detected Latched (RLPDL)
This bit is set when a packet larger than the maximum
packet size is detected.
Bit 2: Receive FCS Errored Packet Count Latched (REPCL)
This bit is set when the REPC bit in the RPPSR
register transitions from zero to one.
Bit 1: Receive Aborted Packet Count Latched (RAPCL)
This bit is set when the RAPC bit in the RPPSR
register transitions from zero to one.
Bit 0: Receive Size Violation Packet Count Latched (RSPCL)
This bit is set when the RSPC bit in the RPPSR
register transitions from zero to one.
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