
ARM946E-S Microprocessor Core with Cache Technical Manual
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
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Contents
Chapter 1
Introduction
1.1
1.2
About the ARM946E-S
Microprocessor Block Diagram
1.2.1
ARM9E-S Processor Core
1.2.2
System Controller
1.2.3
CP15 System Control Coprocessor
1.2.4
Data and Instruction Caches and Control
1.2.5
Protection Unit
1.2.6
Instruction and Data SRAMs
1.2.7
AHB Interface Unit and Write Buffer
1.2.8
External Coprocessor Interface
1.2.9
JTAG and Debug Interface Port
1.2.10
Embedded Trace Module Interface
CoreWare
Program
1-1
1-2
1-4
1-4
1-4
1-5
1-5
1-5
1-5
1-6
1-6
1-6
1-6
1.3
Chapter 2
Signal Descriptions
2.1
Signal Properties and Requirements
2.2
Clock Interface Signals
2.3
AHB Signals
2.4
Instruction RAM Signals
2.5
Data RAM Signals
2.6
Instruction Cache Signals
2.7
Data Cache Signals
2.8
Coprocessor Interface Signals
2.9
Debug Signals
2.10
JTAG Signals
2.11
Miscellaneous Signals
2.12
ETM Interface Signals
2.13
ATPG Scan Control Signals
2-1
2-5
2-5
2-8
2-10
2-11
2-15
2-20
2-22
2-24
2-25
2-25
2-30