
3-12
Programmer’s Model
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
DLM
Data RAM Load Mode
When this bit is set to 1, you can use the data RAM load
mode for initializing the data RAM. First, do a load data
into ARM registers from either the data cache or main
memory. Then store the data from the ARM registers into
the tightly coupled data RAM using the same address
from which the data originated. The operation of the load
mode is described in
Section 6.2.3, “I-SRAM Load Mode,”
on page 6-3
.
17
At reset, this bit is cleared.
DRE
Data RAM Enable
When this bit is set to 1, the data RAM is enabled. Then
the data RAM takes precedence over the data cache and
AHB for data accesses.
16
At reset, this bit is cleared.
CDL
Configure Disable Loading TBIT
This bit controls the behavior of load PC instructions.
When cleared to 0, the ARMv5TExP-specific behavior is
enabled, and bit 0 of the loaded data controls the entry
into the Thumb state when the PC (r15) is the destination
register. When set to 1, this ARMv5TExP behavior is
disabled.
15
At reset, this bit is cleared.
RR
Round-Robin Replacement
This bit controls the cache replacement algorithm. When
set to 1, round-robin replacement is used. When cleared
to 0, a pseudo-random replacement algorithm is used.
14
At reset, this bit is cleared.
AVS
Alternate Vectors Select
This bit controls the base address used for the exception
vectors. When cleared to 0, the base address for the
exception vectors is 0x00000000. When set to 1, the
base address is 0xFFFF0000.
13
Note:
This bit is initialized to either 1 or 0 during system reset,
depending on the value of the input pin, VINITHI. This
allows you to define the exception vector location during
reset to suit the boot mechanism of the application. You
can then reprogram this bit as required following system
reset.