
Debug Using the Serial Interface and TAP Controller
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
9-17
9.3.4 Debug Access to the Caches
It is useful for the debugger to examine the instruction and data cache
contents during debug operations. This examination requires two steps:
1.
The debugger determines if valid addresses are stored in the cache
and forms tag addresses from the tag contents and the tag index.
2.
The debugger uses the generated addresses either to access main
memory or to read individual entries using the CP15 scan chain.
Step 1 –
To do this step, the debugger reads the I-cache and D-cache
tag arrays using scan chain 15. The debugger must do this for each entry
set within the cache.
Figure 9.4
shows the format of the return data.
Figure 9.4
Tag Address Format
The tag address is formed from the tag contents and the tag index. This
combination ensures that the format of the return data is consistent
regardless of cache size.
Step 2 –
Reading individual entries using the CP15 scan chain is useful
if an entry is marked dirty, because this indicates an inconsistency
between the cache contents and main memory.
For the D-cache, the debugger can execute system speed accesses that
hit in the cache and return the cache contents. Writes to the D-cache
from the processor core using this method cause the dirty bits to set for
write-back regions, and main memory is updated for write-through
regions.
If the CP15 scan chain is used for updating the D-cache, only the cache
contents are updated. Writes are not made to main memory. With this
method, you must first program the index/set register with the required
cache index, set, and word values.
Figure 9.5
shows the Cache Index
register format.
31
5
4
3
2
1
0
Tag Address
Valid
Dirty
1
Dirty
2
Set
1
Set
0