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參數(shù)資料
| 型號(hào)： | ARM946E-S |
| 英文描述： | ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
| 中文描述： | ARM946E之，禳微處理器核心與緩存技術(shù)手冊(cè)6月1日 |
| 文件頁(yè)數(shù)： | 162/202頁(yè) |
| 文件大小： | 1395K |
| 代理商： | ARM946E-S |
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9-24
Debug Interface
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
signal is ORed with the internally generated Breakpoint signal before
being applied to the ARM9E-S core control logic. The timing of the input
makes it unlikely that data-dependent external breakpoints can occur.
A breakpointed instruction can enter the execute stage of the pipeline,
but state changes that normally occur from executing the instruction are
inhibited. All writes from previous instructions complete as usual.
The decode cycle of the debug entry sequence occurs during the
execute cycle of the breakpointed instruction. The latched Breakpoint
signal forces the processor to start the debug sequence.
9.5.2 Breakpoints and Exceptions
A breakpointed instruction can have a Prefetch Abort associated with it.
If so, the Prefetch Abort takes priority and the breakpoint is ignored. It is
ignored, because if there is a Prefetch Abort, the instruction data might
be invalid and the breakpoint could be data-dependent. Since the data
could be incorrect, the breakpoint might have triggered incorrectly.
SWI and undefined instructions are treated the same as any other
instruction that might incur a breakpoint. Therefore, the breakpoint takes
priority over the SWI or undefined instruction.
On an instruction boundary, if there is a breakpointed instruction and an
interrupt (nIRQ or nFIQ), the interrupt is taken and the breakpointed
instruction is discarded. After the interrupt is serviced, the execution flow
is returned to the original program. The previously breakpointed
instruction is fetched again. If the breakpoint is still set, the processor
enters the debug state when it reaches the pipeline execute stage.
After the processor enters the halt mode debug state, it is important that
additional interrupts not affect the instructions executed. For this reason,
interrupts are disabled as soon as the processor enters the halt mode
debug state. However, the state of the I and F bits in the Program Status
Register (PSR) are not affected.
9.5.3 Watchpoints
Entry into the debug state following a watchpointed memory access is
imprecise, because of the nature of the pipeline.
相關(guān)PDF資料 |
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| ARM966E-S | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| ARS2569 | Amplifier. Other |
| AR2569 | Amplifier. Other |
| ARS4019 | Amplifier. Other |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM966E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| ARM9DIMM-LPC3250 | 功能描述:模塊化系統(tǒng) - SOM LPC3250 ARM9 DIMM Module, Rev 1.0 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲(chǔ)容量:8 MB, 16 MB 存儲(chǔ)類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in |
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