
Debug Using the Serial Interface and TAP Controller
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
9-5
debug has been completed, the ARM9E-S restores the processor and
system state, and resumes program execution.
The examination of the internal state of the ARM946E-S uses a
JTAG-style interface that allows the serial insertion of instructions into the
instruction pipeline, and exports the contents of the ARM9E-S core
registers. The exported data is serially shifted out without affecting the
rest of the system.
In addition, the ARM9E-S supports a real-time debug mode, where
instead of generating a breakpoint or watchpoint, an internal Instruction
Abort or Data Abort is generated. This mode is known as
monitor mode
operation.
When used in conjunction with a debug monitor program activated by the
abort exception entry, you can debug the ARM946E-S while allowing the
execution of critical interrupt service routines. The debug monitor
program typically communicates with the debug host over the
ARM946E-S debug communication channel. Real-time debug is
described in
Section 9.7, “Real-Time Debug,” page 9-28
.
9.3 Debug Using the Serial Interface and TAP Controller
The JTAG Interface includes six serial registers and a TAP controller
state machine.
9.3.1 Serial Registers
The JTAG interface includes the following serial registers:
Boundary Scan Register
Contains boundary scan data.
Bypass Register
A one-bit shift register that contains test data.
Device ID Code Register
The content of this register identifies the device. TAPID[31:0] drive
this register. Tie these signals to a constant value that represents the
unique device ID code.