
3-2
Programmer’s Model
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
instructions, and are described in
Section 3.3, “CP15 Registers,” on
page 3-2
.
Registers and operations provided by any coprocessors attached to the
external coprocessor interface are accessible with appropriate
coprocessor instructions.
3.2 About the ARM9E-S Programmer’s Model
The ARM9E-S processor core implements the ARMv5TExP architecture,
which includes the 32-bit ARM instruction set and the 16-bit Thumb
instruction set. For a description of both instruction sets, see the
ARM
Architecture Reference Manual
. Contact ARM for complete descriptions
of both instruction sets.
The ARM9E-S uses the
base restored Data Abort model
, which differs
from the
base updated Data Abort model
implemented by ARM7TDMI.
The difference in the ARM9E-S Data Abort model affects only a very
small section of operating system code, the Data Abort handler. It does
not affect user code. With the
base restored Data Abort model
, when a
Data Abort exception occurs during the execution of a memory access
instruction, the processor hardware always restores the base register to
the value it had
before
the instruction was executed. This action
eliminates the requirement that the Data Abort handler
unwind
any base
register update the aborted instruction might have caused.
The
base restored Data Abort model
significantly simplifies the Data
Abort handler software.
3.3 CP15 Registers
The ARM946E-S incorporates CP15 for system control. CP15 allows
configuration of the caches, tightly coupled SRAM, protection unit, write
buffer, and other ARM946E-S system options—such as big- or
little-endian operation.
Table 3.1
shows the CP15 register map.