
Overlapping Regions
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
5-3
is programmed for a given region, the base address must be a multiples
of 8 Kbytes.
Note:
If the region is not aligned correctly, it causes unpredictable
behavior.
5.3.2 Region Size
The region size is specified as a five-bit value, encoding a range of
values from 4 Kbytes to 4 Gbytes. For a detailed list of the bit encodings,
refer to
page 3-20
.
5.3.3 Partition Attributes
Each region has a number of attributes associated with it. These control
how a memory access is performed when the processor core issues an
address that falls within a given region. The attributes are:
Cacheable
Bufferable (for data regions only)
Read/write permissions
To specify this information, program CP15 registers 2, 3, and 5 (see
Chapter 3, “Programmer’s Model”
). If an access fails its protection check
(for example, if a User mode application attempts to access a
Privileged
mode access only
region), a memory abort occurs. The processor enters
the abort exception mode, branching to the Data Abort or Prefetch Abort
vector accordingly.
The cacheable and bufferable bits in CP15 registers 2 and 3 are used
together to select one of four cache and write buffer configurations.
These are described in
Section 7.5, “Write Buffer,” page 7-10
.
5.4 Overlapping Regions
You can program the Protection Unit with two or more overlapping
regions. When overlapping regions are programmed, a fixed priority
scheme is applied to determine the overlapping region attribute that is
applied to the memory access. Attributes for region 7 have the highest
priority, and those for region 0 have the lowest priority.