
9-20
Debug Interface
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
You can program one or both watchpoint units to halt the execution of
instructions by the core. Execution halts when the values programmed
into EmbeddedICE-RT match the values currently appearing on the
address bus, data bus, and various control signals.
Note:
You can mask bits so that their values do not affect the
comparison.
You can configure each watchpoint unit to be either a watchpoint
(monitoring data accesses) or a breakpoint (monitoring instruction
fetches). Watchpoints and breakpoints can be data-dependent in halt
mode debug.
9.4.1 Disabling EmbeddedICE-RT
To disable EmbeddedICE-RT, set the DBGEN input LOW.
Note:
Hardwiring the DBGEN input LOW
permanently
disables
debug access.
When DBGEN is LOW, it inhibits DBGDEWPT, DBGIEBKPT, and
EDBGRQ to the core, and DBGACK from the ARM946E-S is always
LOW.
9.4.2 Debug Communications Channel
The ARM9E-S EmbeddedICE-RT logic contains a communications
channel for passing information between the target and the host
debugger. This channel is implemented as coprocessor 14.
The communications channel consists of:
A 32-bit comms data read register
A 32-bit comms data write register
A 6-bit comms control register for synchronized handshaking
between the processor and the asynchronous debugger
These registers are located in fixed locations in the EmbeddedICE-RT
logic register map and are accessed from the processor using MCR and
MRC instructions to coprocessor 14.
In addition to the comms channel registers, the processor can access a
1-bit debug status register for use in the real-time debug configuration.