
ARM9E-S Clock Domains
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
9-29
Because the monitor mode debug does not put the processor into the
debug state, you must change the contents of the watchpoint registers
while external memory accesses are taking place. If the watchpoint
registers are updated during a memory access, all matches from the
affected watchpoint unit using the register are disabled for that update
cycle.
If false matches can occur during changes to the watchpoint registers
(due to old data in some registers and new data in others), then you must
do the following:
1.
Disable the watchpoint unit using the Control register for that
watchpoint unit.
2.
Change the other registers.
3.
Re-enable the watchpoint unit by rewriting the Control register.
9.8 ARM9E-S Clock Domains
The ARM9E-S processor has a single clock, CLK, that is qualified by two
clock enables:
SYSCLKEN controls access to the memory system
DBGTCKEN controls debug operations
During normal operation, SYSCLKEN conditions CLK to clock the
processor. When the ARM946E-S is in the debug state, DBGTCKEN
conditions CLK to clock the processor.
9.9 Synchronizing Debug Clocks
The ARM Multi-ICE debug agent directly supports one or more cores
within an ASIC design.
External synchronization is required for the system debug and test clock
inputs to the ARM946E-S. To synchronize the ARM946E-S with off-chip
debug clocking, you must use a three-stage synchronizer. The off-chip
device (for example, Multi-ICE) issues a TCK signal, and waits for the
Returned TCK (RTCK) signal to come back. Synchronization is
maintained because the off-chip device does not progress to the next
TCK until after RTCK is received.