
6-4
Tightly Coupled SRAM
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
A suggested assembler code sequence for this procedure is shown
below:
MOV R0, #0
LDR R1, =ImageTop
MRC p15, 0, R2, c1, c0, 0 ; Read Control Register
ORR R2, R2, #&C0000
MCR p15, 0, R2, c1, c0, 0 ; Enable Instruction RAM and Load Mode CopyLoop
LDMIA R0, {R2 - R9}
; Load 8 registers from main memory
STMIA R0!, {R2 - R9}
; Store 8 regs into instruction SRAM
CMP R1, R0
; Check if limit reached
BGT CopyLoop
; Repeat if more to do
; Initialize pointer
; Define end of code image
The read (LDMIA) accesses external memory or the data cache, and the
write (STMIA) updates the tightly coupled I-SRAM.
Do not use SWP or SWPB to access I-SRAM addresses while in load
mode. Doing this produces unpredictable results.
6.2.4 Enabling and Disabling the D-SRAM
To enable the D-SRAM, set bit 16 of the CP15 Control register. See
Section 3.3, “CP15 Registers,” page 3-2
for details of how to read and
write this register. After the D-SRAM is enabled, all read and write
accesses to the D-SRAM address space access the D-SRAM.
To disable the D-SRAM, clear bit 16 of the CP15 control register. After
you disable the D-SRAM, all reads and writes to the D-SRAM address
space access the AHB.
Reads and writes to D-SRAM address space either use the D-SRAM or
access the AHB depending on whether D-SRAM is enabled or not.
For more information, see
Section 3.3.12, “Tightly Coupled Memory
Region Registers (9),” page 3-26
.
6.2.5 D-SRAM Load Mode
You must initialize the D-SRAM with the required data image before use.
To initialize the D-SRAM, write to it from the ARM9E-S processor core
data interface.