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Microprocessor Block Diagram
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
1-5
1.2.4 Data and Instruction Caches and Control
The ARM946E-S has separate data and instruction caches. Each cache
is direct mapped, or either 2-way or 4-way set associative. The D-cache
and I-cache use a physical address from the processor core, and have
a cache update policy of
allocate on a read miss
. The D-cache and
I-cache are reloaded one cache line (eight words) at a time through the
external interface.
Refer to Chapter 4 for more information about the data and instruction
caches.
1.2.5 Protection Unit
The Protection Unit makes it possible to partition memory into eight
regions of variable size and to set individual attributes for each memory
region.
Refer to Chapter 5 for more information about the Protection Unit.
1.2.6 Instruction and Data SRAMs
The ARM946E-S incorporates internal instruction and data memories to
allow high-speed operation without incurring the performance penalties
of accessing the system bus. The Instruction and Data RAMs each
consist of blocks of ASIC library compiled RAM. The RAM sizes can be
of any size up to 1 Mbyte. The instruction and data memories can have
different sizes.
Refer to Chapter 6 for more information about the Instruction and Data
RAMS.
1.2.7 AHB Interface Unit and Write Buffer
The Advanced High-Performance Bus (AHB) is a new generation of
AMBA bus, which meets the requirements of high-performance
synthesizable designs. The AHB Interface Unit arbitrates between the
sources of external bus transactions within the ARM946E-S. It stalls all
other accesses until the current request has been completed.
The Write Buffer is a 16-entry FIFO. It increases system performance.