- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362398 > ARM946E-S ARM946E-S Microprocessor Core with Cache technical manual 6/01 PDF資料下載
參數(shù)資料
| 型號(hào)： | ARM946E-S |
| 英文描述： | ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
| 中文描述： | ARM946E之，禳微處理器核心與緩存技術(shù)手冊(cè)6月1日 |
| 文件頁(yè)數(shù)： | 121/202頁(yè) |
| 文件大?。?/td> | 1395K |
| 代理商： | ARM946E-S |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)當(dāng)前第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)
AHB Clocking
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
7-7
7.4 AHB Clocking
The ARM946E-S design uses a single rising-edge clock (CLK) to time all
internal activity. Some systems in which the ARM946E-S is embedded
might need to run the AHB at a lower rate. To support this requirement,
the ARM946E-S requires a clock enable (HCLKEN) to time AHB
transfers.
The HCLKEN input is driven HIGH coincident with a rising edge of the
ARM946E-S CLK. This action indicates that this particular rising-edge is
also an HCLK rising-edge. HCLK must be synchronous with the
ARM946E-S CLK.
When the ARM9E-S processor is running from tightly coupled SRAM or
performing writes using the write buffer, the ARM946E-S HCLKEN and
HREADY inputs are not used to stall the ARM9E-S processor. The
processor only stalls when there are SRAM stall cycles or if the write
buffer overflows. This means that the ARM9E-S is executing instructions
at the faster CLK rate and is effectively decoupled from the HCLK
domain.
However, when an AHB read access or unbuffered write occurs, the core
does stall until the AHB transfer is completed. While the lower rate HCLK
clocks the AHB system, HCLKEN is examined to determine when to
drive out the AHB address and control that start an AHB transfer.
HCLKEN then must detect the next rising edge of HCLK, so the BIU
knows when the access is complete.
If the slave being accessed at the HCLK rate has a multicycle response,
the HREADY input to the ARM946E-S is driven LOW until the data is
ready to return. The BIU must do a logical AND on the HREADY
response with HCLKEN to detect when the AHB transfer is completed
.
When the transfer is completed, SYSCLKEN is reasserted and enables
the processor.
Note:
When an AHB access is required, the processor core is
stalled until the next HCLKEN pulse is received. The
processor is stalled twice, once before it starts the access
and while waiting for the access to finish. The stall before
the start of the access is a synchronization penalty, and the
worst case can be expressed in CLK cycles as the
HCLK-to-CLK ratio minus 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ARM966E-S | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| ARS2569 | Amplifier. Other |
| AR2569 | Amplifier. Other |
| ARS4019 | Amplifier. Other |
| AR4019 | Amplifier. Other |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM966E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| ARM9DIMM-LPC3250 | 功能描述:模塊化系統(tǒng) - SOM LPC3250 ARM9 DIMM Module, Rev 1.0 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲(chǔ)容量:8 MB, 16 MB 存儲(chǔ)類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。