
9-28
Debug Interface
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
9.7 Real-Time Debug
The ARM9E-S processor contains logic that permits you to debug a
system without completely stopping the processor. This allows servicing
critical interrupt routines to continue while the debugger interrogates the
processor. Setting bit 4 of the Debug Control register enables the
ARM9E-S real-time debug features. When set, this bit configures the
EmbeddedICE-RT logic so a breakpoint or watchpoint causes the
processor to enter abort mode and take the Prefetch Abort or Data Abort
vectors, respectively.
The following restrictions apply when the ARM9E-S processor is
configured for real-time debugging:
Breakpoints/watchpoints cannot be data-dependent. No support is
provided for the range and chain functionality.
Breakpoints/watchpoints are based only on:
–
Instruction/data addresses
–
External watchpoint conditioner (DBGEXTERN)
–
User/privileged mode access (DnTRANS/InTRANS)
–
Read/write access (watchpoints)
–
Access size (breakpoints: ITBIT, watchpoints: DMAS[1:0]).
Single-step hardware is not enabled.
External breakpoints/watchpoints are not supported.
Use the vector catching hardware, but you must not configure it to
catch the Prefetch or Data Abort exceptions.
No support is provided for mixing halt mode/monitor mode debug
functionality. When the processor is configured for monitor mode,
asserting the external EDBGRQ signal or setting the internal
EDBGRQ bit causes unpredictable behavior.
If an abort is generated in monitor mode, the abort is recorded in the
CP14 Debug Status register (bit 0). For more information about this
register, including its format and bit definitions, see
Section 3.4.2, “Debug
Status Register (C2)”
in this manual.