
CP15 Registers
Copyright 2000–2001 by LSI Logic Corporation. All rights reserved.
3-13
IE
I-Cache Enable
This bits controls I-cache behavior.
12
To use the instruction cache, both the protection unit
enable bit (bit 0) and the I-cache enable bit must be set
to 1. You can do this with a single write to register 1.
At reset, this bit is cleared.
EDN
Endian
This bit selects the endian configuration of the
ARM946E-S. When this bit is set to 1, the big-endian
configuration is selected. When cleared to 0, the
little-endian configuration is selected.
7
At reset, this bit is cleared.
RWO
Reserved - Write Ones
This field is reserved. Write ones to these bits.
[6:3]
DE
D-Cache Enable
This bit controls the behavior of the D-cache.
2
To use the data cache, both the protection unit enable bit
(bit 0) and the D-cache enable bit must be set to 1. This
can be done with a single write to register 1.
At reset, this bit is cleared.
PE
Protection Unit Enable
This bit controls the operation of the ARM946E-S
Protection Unit.
0
At reset, this bit is cleared, which disables the Protection
Unit. It also disables the instruction cache, data cache,
and the write buffer.
At least one protection region must be programmed
before the Protection Unit is enabled. See
Section 3.3.9,
“Protection Region/Base Size (PR/BS) Registers (6),” on
page 3-19
and
Chapter 3, “Programmer’s Model.”
3.3.6 Cache Configuration Registers (2)
These registers contain the cacheable attributes for the eight memory
regions. Individual control is provided for the I and D caches. If the
opcode_2 field = 0, then the data cache bits are programmed. If the
opcode_2 field = 1, then the instruction cache bits are programmed. To
read and write these registers: