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9-22
Debug Interface
Copyright 2000-2001 by LSI Logic Corporation. All rights reserved.
The debugger sees both the R and W bits when it polls the Debug
Comms Control register through the JTAG interface. When the debugger
sees that the W bit is set, it can read the Comms Data Write register,
and scan the data out. The action of reading this data register clears the
Debug Comms Control register W bit. At this point, the communications
process can begin again.
9.4.4.2 Receiving a Message from the Debugger
Transferring a message from the debugger to the processor is similar to
sending a message to the debugger. In this case, the debugger polls the
R bit of the Debug Comms Control register.
If the R bit is LOW, the Comms Data Read register is free, and data
can be placed there for the processor to read.
If the R bit is set, previously deposited data has not yet been
collected, so the debugger must wait.
When the Comms Data Read register is free, data is written there using
the JTAG interface. The action of this write sets the R bit in the Debug
Comms Control register.
The processor polls the Debug Comms Control register. If the R bit is
set, there is data that can be read using an MRC instruction to
coprocessor 14. The action of this load clears the R bit in the Debug
Comms Control register. When the debugger polls this register and sees
that the R bit is clear, the data has been taken, and the process can now
be repeated.
9.5 Breakpoints, Watchpoints, and Debug Requests
Breakpoints, watchpoints, and external debug requests can cause the
ARM946E-S to enter the debug state. These events are associated with
the following debug interface signals:
DBGIEBKPT, DBGDEWPT, and EDBGRQ are system requests for
the ARM946E-S to enter the debug state. The three signals indicate
an instruction breakpoint, data watchpoint, and external debug
request, respectively. All three originate from hardware external to
the ARM946E-S.