參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 97/116頁
文件大?。?/td> 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
4-17
Functional Description
When EDO DRAM is used, the 82443ZX will open at most one page at a time. That is, one RAS#
line will be asserted at any time. When SDRAM is used, either 2 or 4 pages can be open at any time
within any row. If a row contains SDRAMs based on 16Mb technology (i.e., 12x8/9/10 devices)
then two pages can be open at a time within that row. If a row contains SDRAMs based on 64Mb
technology, (i.e., 14x8/9/10 devices) then four pages can be open at a time within that row.
This address multiplexing scheme is derived from Table 4-11 which depicts the addressing
requirements for each of the row/column organizations for each row size. The SDRAM
components used for the options shown in the table are as follows:
Option
2 (16MB)
4 (64MB)
SDRAM Component Type
2Mx8
8Mx8
Table 4-10. Supported Memory Configurations
DRAM Attributes
DRAM DIMM
DRAM
Addressing
MA
DRAM
Size
Type
Tech
Depth
Width
SS x64
DS x64
Row
Col
Banks
Min
(1 row)
EDO
4M
1M
4
1M
2M
Symmetric
10
10
NA
8 MB
1M
4
1M
2M
Asymmetric
11
9
NA
8 MB
EDO
16M
2M
8
2M
4M
Asymmetric
11
10
NA
16 MB
2M
8
2M
4M
Asymmetric
12
9
NA
16 MB
2M
8
2M
4M
Asymmetric
13
8
NA
16 MB
4M
4
4M
8M
Symmetric
11
11
NA
32 MB
4M
4
4M
8M
Asymmetric
12
10
NA
32 MB
4M
4
4M
8M
Asymmetric
14
8
NA
32 MB
EDO
64M
4M
16
4M
8M
Symmetric
11
11
NA
32 MB
4M
16
4M
8M
Asymmetric
12
10
NA
32 MB
4M
16
4M
8M
Asymmetric
14
8
NA
32 MB
8M
8
8M
16M
Asymmetric
12
11
NA
64 MB
16M
4
16M
32M
Symmetric
12
12
NA
128 MB
SDRAM
16M
2M
8
2M
4M
Asymmetric
12
9
2
16 MB
2M
8
2M
4M
Asymmetric
13
8
2
16 MB
SDRAM
64M
4M
16
4M
8M
Asymmetric
14
8
4
32 MB
4 bank
8M
8
8M
16M
Asymmetric
14
9
4
64 MB
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