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參數(shù)資料
| 型號(hào)： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁(yè)數(shù)： | 90/116頁(yè) |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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Functional Description
4-10
82443ZX Host Bridge Datasheet
4.1.5.3
Legacy VGA Ranges
The legacy VGA memory range A0000h–BFFFFh is mapped either to PCI or to AGP depending
on the programming of the BCTRL configuration register in 82443ZX Device #1 configuration
space, and the NBXCONF (MDAP bit) configuration register in Device #0 configuration space.
The same registers control mapping of VGA I/O address ranges. VGA I/O range is defined as
addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA
address aliases - A[15:10] are not decoded).
4.2
Host Interface
The host interface of the 82443ZX is optimized to support the Pentium II processor with bus clock
frequencies of 100 MHz and 66/60 MHz. The 82443ZX implements the host address, control, and
data bus interfaces within a single device. Host bus addresses are decoded by the 82443ZX for
accesses to main memory, PCI memory, PCI I/O, PCI configuration space and AGP space
(memory, I/O and configuration). The 82443ZX takes advantage of the pipelined addressing
capability of the Pentium II processor to improve the overall system performance.
4.2.1
Host Bus Device Support
The 82443ZX recognizes and supports a large subset of the transaction types that are defined for
the Pentium II processor bus interface. However, each of these transaction types have a multitude
of response types, some of which are not supported by this controller. All transactions are
processed in the order that they are received on the Pentium
II processor bus. Table 4-5
summarizes the transactions supported by the 82443ZX.
Topic
Definition
AGP IO
range
The AGP bus can be allocated with 1 block of IO space with a granularity of 4KB. The IO base
address register points to the beginning of the AGP IO range while IO limit address register
points to the end of this range. The IO range definition is based on the PCI to PCI specification.
ISA_EN
The ISA_EN bit in the 82443ZX device1 is necessary in ISA bus based systems where there is a
need to allocate IO space to AGP bus devices. This is necessary since legacy ISA devices
decode IO range of address [9:0] only and thus the IO address of the devices are aliased for
every 1 KB of the 64 KB IO range. Therefore, to provide IO range to AGP bus and maintain the
ISA IO legacy rules, the ISA_EN is set. As a result, all CPU cycles in the address ranges:
“xxxx_xx01_0000_0000”b to “xxxx_xx11_1111_1111”b, that is the top 768 bytes of each 1KB
aligned block, are sent to the PCI bus independent of whether this particular address is inside or
outside the range allocated to the AGP bus.
The above is relevant only to CPU-initiated cycles, as PCI and AGP master IO cycles are never
claimed by the 82443ZX. The ISA_EN functional definition is based on the PCI to PCI
specification.
VGA_EN
VGA IO range is defined in the following ranges: 3B0-3BBh, 3C0-3DFh. When the VGA_EN is
set, all CPU initiated IO cycles in the VGA IO range are forwarded to the AGP bus, independent
of whether the ISA_EN bit is set or not. Thus the VGA_EN bit setting takes precedence relative
to the setting of the ISA_EN bit. The VGA_EN functional definition is based on the PCI to PCI
specification.
MDAP
The MDA IO range includes the ports 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh. Once the VGA_EN
is set, it is legal to set the MDAP bit to indicate that a second CRT controller (Monochrome
Display Adapter) resides in the PCI or ISA bus. In this case, all the CPU-initiated IO cycles in the
VGA range that are not in to the above ports are sent to AGP bus while the cycles to the above
six IO ports (and to all the aliased ports) are sent to PCI bus.
Note that the CPU IO cycles to the above ports are sent to AGP bus independent of the AGP IO
range and ISA_EN setting.
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