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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 86/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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Functional Description
4-6
82443ZX Host Bridge Datasheet
Note:
The 82443ZX Device #1 memory range registers described above are used to allocate memory
address space for any devices on AGP that require such a window. These devices include the AGP
compliant device, and multifunctional AGP compliant devices where one or more functions are
implemented as PCI devices.
4.1.1.4
AGP DRAM Graphics Aperture
Memory-mapped, graphics data structures can reside in a
Graphics Aperture
to main DRAM
memory
.
This aperture is an address range defined by the APBASE configuration register of the
82443ZX Host Bridge. The APBASE register follows the normal base address register template as
defined by the PCI 2.1 specification. The size of the range claimed by the APBASE is programmed
via “back-end” register APSIZE (programmed by the chip-set specific BIOS before plug-and-play
session is performed). APSIZE allows selection of the aperture size of 4 MB, 8 MB,16 MB,
32 MB, 64 MB, 128 MB and 256 MB. By programming APSIZE to a specific size, the
corresponding lower bits of APBASE are forced to “0” (behave as hardwired). Default value of
APSIZE forces aperture size of 256 MB. Aperture address range is naturally aligned.
Although this aperture appears to be established in PCI memory space, in fact the 82443ZX
forwards accesses within the aperture range to the main DRAM subsystem. The originally issued
addresses are translated (within 82443ZX’s DRAM controller subsystem) via a translation table
maintained in main memory. Translation table entries may be partially cached in a Graphics
Translation Look-aside Buffer (GTLB) implemented within the 82443ZX’s DRAM subsystem.
The aperture range will not be cacheable in the processor caches.
4.1.1.5
System Management Mode (SMM) Memory Range
82443ZX supports the use of main memory as System Management RAM (SMRAM) enabling the
use of System Management Mode. The 82443ZX supports two SMRAM options: Compatible
SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM
(SMRAM) space provides a memory area that is available for the SMI handler's and code and data
storage. This memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. The 82443ZX provides three
SMRAM options:
Below 1 MB option that supports compatible SMI handlers.
Above 1 MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
Optional larger write-back cacheable T_SEG area from 128KB to 1MB in size above 1 MB
that is reserved from the highest area in system DRAM memory. The above 1 MB solutions
require changes to compatible SMRAM handlers code to properly execute above 1 MB.
Table 4-2 summarizes the operation of SMRAM space cycles targeting the SMI space addresses.
Note that the 82443ZX supports a maximum of 256MB of memory in 2 DIMM sockets.
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