參數(shù)資料
型號(hào)： 82443ZX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 52/116頁
文件大小： 533K
代理商： 82443ZX
Register Description
3-28
82443ZX Host Bridge Datasheet
3.3.22
ESMRAMC—Extended System Management RAM Control
Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
73h
38h
Read/Write
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 Mbyte.
Bit
Description
7
H_SMRAM_EN (H_SMRAME).
Controls the SMM memory space location (i.e above 1 Mbyte or
below 1 Mbyte).
1 = When G_SMRAME is 1 and H SMRAME is set to 1, the High SMRAM memory space is
enabled, the Compatible SMRAM memory is disabled, and accesses in the 0A0000h to
0FFFFFh range are forwarded to PCI, while SMRAM accesses from 100A0000h to
100FFFFFh are remapped to DRAM address A0000h to FFFFFh
0 = When G SMRAME is set to a 1 and H SMRAM EN is set to 0, then the Compatible SMRAM
space is enabled.
Once D_LCK is set, this bit becomes read only.
6
E_SMRAM_ERR (E_SMERR).
1 = This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High
Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0.
0 = It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it.
5
SMRAM_Cache (SM_CACHE).
This bit is forced to ‘1’ by 82443ZX.
4
SMRAM_L1_EN (SM_L1).
This bit is forced to ‘1’ by 82443ZX.
3
SMRAM_L2_EN (SM_L2).
This bit is forced to ‘1’ by 82443ZX.
2:1
TSEG_SZ[1:0] (T_SZ).
Selects the size of the TSEG memory block, if enabled. This memory is
taken from the top of DRAM space (i.e., TOM - TSEG_SZ), which is no longer claimed by the
memory controller (all accesses to this space are sent to the PCI bus if TSEG_EN is set). The
physical address for the extended SMRAM memory appears is from (256M + TOM - TSEG_SZ) to
(256M + TOM). This address is remapped to DRAM address (TOM - TSEG_SZ) to TOM. This
field decodes as follows:
00 = (TOM–128KB) to TOM
01 = (TOM–256KB) to TOM
10 = (TOM–512KB) to TOM
11 = (TOM–1MB) to TOM
Once D_LCK is set, this bit becomes read only.
0
TSEG_EN (T_EN).
Enabling of SMRAM memory (TSEG, 128 KB, 256 KB, 512 KB or 1 MB of
additional SMRAM memory) for Extended SMRAM space only. When
G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical
address space. Once D_LCK is set, this bit becomes read only.
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