參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 62/116頁
文件大小： 533K
代理商： 82443ZX
Register Description
3-38
82443ZX Host Bridge Datasheet
3.3.34
AGPCTRL—AGP Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
B0–B3h
00000000h
Read/Write
32 bits
This register provides for additional control of the AGP interface.
Bit
Description
31:16
Reserved.
15
Snoopable Writes In Order With AGP Reads Disable (AGPDCD).
When set to 0 (default), the
82443ZX maintains ordering between snoopable write cycles and AGP reads. When set to 1, the
82443ZX handles the AGP reads and snoopable writes as independent streams.
AGPDCD
AGPRSE
Description
(Bit 15)
(Bit 13)
0
0
DWB is visible to AGP reads. DWB flushes only when address hit.
0
1
Illegal.
1
0
Illegal
1
1
DWB flushes when write to AGP occurs
14
Reserved
13
Graphics Aperture Write-AGP Read Synchronization Enable (AGPRSE).
When this bit is set
the 82443ZX will ensure that all writes posted in the Global Write Buffer to the Graphics Aperture
are retired to DRAM before the 82443ZX will initiate any CPU-to-AGP cycle. This can be used to
ensure synchronization between the CPU and AGP master. The AGPDCD bit description defines
the interaction between the AGPRSE bit and the AGPDCD bit.
1 = Enable
0 = Disable (Default)
12:8
Reserved
7
GTLB Enable (and GTLB Flush Control).
1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer.
0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry.
6:0
Reserved.
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