參數(shù)資料
型號(hào)： 82443ZX
廠商： INTEL CORP
元件分類(lèi)： 存儲(chǔ)控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁(yè)數(shù)： 56/116頁(yè)
文件大?。?/td> 533K
代理商： 82443ZX
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Register Description
3-32
82443ZX Host Bridge Datasheet
3.3.26
PMCR—Power Management Control Register (Device 0)
Address Offset:
Default Value:
Access
Size
7Ah
0000_S0S0b
Read/Write
8 Bits
Bit
Description
7
Power Down SDRAM Enable (PDSE).
1 = Enable. When PDSE=1, an SDRAM row in idle state will be issued a power down
command. The SDRAM row will exit power down mode only when there is a request to
access this particular row.
0 = Disable
6
ACPI Control Register Enable (SCRE).
1 = Enable. The ACPI control register in the 82443ZX is enabled, and all CPU cycles to IO
address 0022h are handled by the 82443ZX and are not forwarded to PCI.
0 = Disable (default). All CPU cycles to IO address 0022h are passed on to the PCI bus.
5
Suspend Refresh Type (SRT).
This bit determines what type of EDO DRAM refresh is used
during Power On Suspend (POS/STR) or Suspend to RAM modes. SRT has no effect on
SDRAM refresh.
1 = Self refresh mode
0 = CBR fresh mode
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
4
Normal Refresh Enable (NREF_EN).
This bit is used to enable normal refresh operation
following a POS/STR state. After coming out of reset
the software must set this bit before
doing an access to memory.
1 = Enable
0 = Disable
3
Quick Start Mode (QSTART) (RO).
1 = Quick start mode of operation is enabled for the processor. This mode is entered using a
strapping option that is sampled by the 82443ZX and the CPU during reset. This register
bit is Read Only and a configuration write to it is ignored.
2
Gated Clock Enable (GCLKEN).
GCLKEN enables internal dynamic clock gating in the
82443ZX when a AGPset “IDLE” state occurs. This happens when the 82443ZX detects an
idle state on all its buses.
1 = Enable
0 = Disable
1
AGP Disable (AGP_DIS).
This register bit is Read Only and a configuration write to it is
ignored.
1 = Disable. The AGP interface and the clocks of AGP associated logic are permanently
disabled. This mode is entered using a strapping option that is sampled by the 82443ZX
during reset.
0 = Enable
0
CPU reset without PCIRST enable (CRst_En).
This bit enables the 82443ZX to assert CPU
reset without an incoming PCIRST#. This option allows the reset of the processor when the
system is coming out of POS state. Defaults to ‘0’ upon PCIRST# assertion.
1 = Enable
0 = Disable
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
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