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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 25/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
3-1
Register Description
Register Description
3
The 82443ZX contains two sets of software accessible registers, accessed via the Host CPU I/O
address space:
1. Control registers that are I/O mapped into the CPU I/O space. These registers control access to
PCI and AGP configuration space.
2. Internal configuration registers residing within the 82443ZX, partitioned into two logical
device register sets (“l(fā)ogical” since they reside within a single physical device). The first
register set is dedicated to Host-to-PCI Bridge functionality. This set (device 0) controls PCI
interface operations, DRAM configuration, and other chip-set operating parameters and
optional features. The second register set (device 1) is dedicated to Host-to-AGP Bridge
functions (controls AGP interface configurations and operating parameters).
The following nomenclature is used for register access attributes.
The 82443ZX supports PCI configuration space access using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.
The 82443ZX internal registers (both I/O Mapped and Configuration registers) are accessible by
the Host CPU. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities,
with the exception of CONFADD which can only be accessed as a Dword. All multi-byte numeric
fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the
field).
Some of the 82443ZX registers described in this section contain reserved bits. These bits are
labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads, software
must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit positions are
preserved. That is, the values of reserved bit positions must first be read, merged with the new
values for other bit positions and then written back.
Note:
Software does not need to perform read, merge, write operation for the configuration address
register.
In addition to reserved bits within a register, the 82443ZX contains address locations in the
configuration space of the Host-to-PCI Bridge entity that are marked either "Reserved" or “Intel
Reserved”. The 82443ZX responds to accesses to “Reserved” address locations by completing the
host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved”
registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the
RO
Read Only
. If a register is read only, writes to this register have no effect.
R/W
Read/Write
. A register with this attribute can be read and written
R/WC
Read/Write Clear
. A register bit with this attribute can be read and written.
However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has
no effect.
R/WO
Read/Write Once.
A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only.
R/WL
Read/Write/Lock.
This register includes a lock bit. Once the lock bit has been set to
1, the register becomes read only.
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