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參數(shù)資料
| 型號(hào)： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁(yè)數(shù)： | 57/116頁(yè) |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
3-33
Register Description
3.3.27
SCRR—Suspend CBR Refresh Rate Register (Device 0)
Address Offset:
Default Value:
Access
Size
7Bh–7Ch
0038h
Read/Write
16 Bits
3.3.28
EAP—Error Address Pointer Register (Device 0)
Address Offset:
Default Value:
Access
Size
80–83h
00000000h
Read Only, Read/Write-Clear
32 Bits
Bit
Description
15:13
Reserved.
12
Suspend CBR refresh Rate Auto Adjust Enable (SRRAEN).
SRRAEN bit is cleared to its default
during cold reset only. It is not affected by PCIRST# during resume from suspend.
0 = Disable (default). Indicates that the suspend CBR refresh rate is not updated by the 82443ZX
hardware to track the system operating conditions. In this case, it is expected that BIOS will set
the SRR to reflect the worst case operating conditions so that minimum refresh rate will be
provided.
1 = Enable. Indicates that the 82443ZX hardware adjusts the suspend refresh rate according to
system operating conditions by comparing the number of OSCCLKs in a given time. This mode
allows the system to dynamically adjust the refresh rate and thus minimize suspend power
consumption while guaranteeing required refresh rate.
11:0
Suspend CBR Refresh Rate (SRR).
The rate is loaded into the counter which counts down on
OSCCLK rising edges. When it expires, a suspend CBR refresh request is triggered. This bit field
may be loaded by BIOS to reflect the desirable refresh rate. In addition, the 82443ZX will update it
automatically, when the above SRRAEN = 1. In either case, the register is accessible for read and
write operation at all times.
This 12-bit field provides a dynamic range greater than the maximum CBR refresh rate that is
supported of 249.6uSEC.
SRR bit field is cleared to its default during cold reset only. It is not affected by PCIRST# during
resume from suspend.
The default value of this register is 038h, or 56 decimal. It represents a 15.5uS time between
refreshes with the slowest corner OSCCLK cycle time of 270nS.
Bit
Description
31:12
Error Address Pointer (EAP) (RO).
This field is used to store the 4 KB block of main memory
of which an error (single bit or multi-bit error) has occurred. Note that this field represents the
address of the first error occurrence after bits 1:0 have been cleared by software. Once bits 1:0
are set to a value different than 00b, as a result of an error, this bit field is locked and doesn't
change as a result of a new error.
11:2
Reserved.
1
Multiple Bit Error (MBE) (R/WC).
This bit indicates that a multi-bit ECC error has occurred,
and the address has been logged in bits 31:12. The EAP register is locked until the CPU
clears this bit by writing a 1. Software uses bits 1:0 to detect whether the logged error address
is for Single or Multi bit error, since both Single and Multiple Error bits of the Error Status
register can be set. Once software completes the error processing, a value of ‘1’ is written to
this bit field to clear the value (back to 0) and unlock the error logging mechanism.
Note: Any ECC errors received during initialization should be ignored.
0
Single Bit Error (SBE) (R/WC).
1 = Indicates that a single bit ECC error has occurred, and the address has been logged in bits
31:12. The EAP register is locked until the CPU clears this bit by writing a 1.
Note: Any ECC errors received during initialization should be ignored.
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