參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 73/116頁
文件大小： 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
3-49
Register Description
3.4.6
SUBC1—Sub-Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Ah
04h
Read Only
8 bits
This register contains the Sub-Class Code for the 82443ZX device #1. This code is 04h indicating a
PCI-to-PCI Bridge device. The register is read only.
3.4.7
BCC1—Base Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class Code of the 82443ZX device #1. This code is 06h indicating a
Bridge device. This register is read only.
3.4.8
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read/Write
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to comply with the normal PCI-to-PCI bridge configuration software.
Bit
Description
7:0
Sub-Class Code (SUBC1).
This is an 8-bit value that indicates the category of Bridge into which
the 82443ZX falls.
04h = Host Bridge.
Bit
Description
7:0
Base Class Code (BASCC).
This is an 8-bit value that indicates the Base Class Code for the
82443ZX device #1.
06h = Bridge device.
Bit
Description
7:3
Not applicable but support read/write operations.
(Reads return previously written data.)
2:0
Reserved.
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