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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 79/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
3-55
Register Description
3.4.21
BCTRL—PCI-to-PCI Bridge Control Register (Device 1)
Address Offset:
Default:
Access:
Size
3Eh
80h
Read/Write
8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., AGP) as well as some bits
that affect the overall behavior of the “virtual” PCI-to-PCI bridge in the 82443ZX (e.g., VGA
compatible address ranges mapping).
Bit
Descriptions
7
Fast Back to Back Enable.
82443ZX supports fast back-to-back cycles on AGP, and therefore
this bit is hardwired to 1.
6
Secondary Bus Reset:
82443ZX does not support generation of reset via this bit on the AGP
and therefore this bit is hardwired to 0.
NOTE: The only way to perform a hard reset of the AGP is via the system reset either initiated by
software or hardware via PIIX4E.
5
Master Abort Mode.
Not applicable. Hardwired to 0. (This means when acting as a master on
AGP the 82443ZX will drop writes on the “floor” and return all 1s during reads.)
4
Reserved.
3
VGA Enable.
Controls the routing of CPU-initiated transactions targeting VGA compatible I/O
and memory address ranges.
1 = 82443ZX will forward the following CPU accesses to AGP:
memory accesses in the range 0A0000h to 0BFFFFh
I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases - A[15:10] are not decoded)
When this bit is set, forwarding of these accesses issued by the CPU is independent of the
I/O address and memory address ranges defined by the previously defined base and limit
registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA
Enable) of this register or of bit 5 (VGA Palette Snoop Enable) of the PCICMD1 register if
this bit is 1.
0 = VGA compatible memory and I/O range accesses are mapped to PCI unless they are
redirected to AGP via I/O and memory range registers defined above (IOBASE, IOLIMIT,
MBASE, MLIMIT, PMBASE, PMLIMIT). (default)
2
ISA Enable.
Modifies the response by the 82443ZX to an I/O access issued by the CPU that
target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE
and IOLIMIT registers.
1 = When this bit is set to 1 82443ZX will not forward to AGP any I/O transactions addressing
the last 768 bytes in each 1KB block even if the addresses are within the range defined by
the IOBASE and IOLIMIT registers. Instead going to AGP these cycles will be forwarded to
PCI where they can be subtractively or positively claimed by the ISA bridge.
0 = All addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions will be mapped
to AGP. (default)
1
Reserved.
0
Parity Error Response Enable.
Controls 82443ZX’s response to data phase parity errors on
AGP. G_PERR# is not implemented by the 82443ZX. However, when this bit is set to 1, address
and data parity errors on AGP are reported via SERR# mechanism, if enabled by SERRE1 and
SERRE. If this bit is reset to 0, then address and data parity errors on AGP are not reported via
the 82443ZX SERR# signal. Other types of error conditions can still be signaled via SERR#
independent of this bit’s state.
1 = Enable.
0 = Disable.
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