參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 5/116頁
文件大小： 533K
代理商： 82443ZX
82443ZX Host Bridge
Datasheet
v
Contents
1
Architectural Overview...............................................................................................1-1
2
Signal Description......................................................................................................2-1
2.1
Host Interface Signals...................................................................................2-1
2.2
DRAM Interface ............................................................................................2-3
2.3
PCI Interface (Primary).................................................................................2-5
2.4
Primary PCI Sideband Interface ...................................................................2-6
2.5
AGP Interface Signals...................................................................................2-7
2.6
Clocks, Reset, and Miscellaneous................................................................2-9
2.7
Power-Up/Reset Strap Options...................................................................2-10
3
Register Description...................................................................................................3-1
3.1
I/O Mapped Registers...................................................................................3-2
3.1.1
CONFADD—Configuration Address Register..................................3-2
3.1.2
CONFDATA—Configuration Data Register .....................................3-3
3.1.3
PM2_CTL—ACPI Power Control 2 Control Register.......................3-4
3.2
PCI Configuration Space Access..................................................................3-4
3.2.1
Configuration Space Mechanism Overview.....................................3-5
3.2.2
Routing the Configuration Accesses to PCI or AGP........................3-5
3.2.3
PCI Bus Configuration Mechanism Overview..................................3-6
3.2.3.1 Type 0 Access ....................................................................3-6
3.2.3.2 Type 1 Access ....................................................................3-6
3.2.4
AGP Bus Configuration Mechanism Overview ................................3-6
3.2.5
Mapping of Configuration Cycles on AGP .......................................3-7
3.3
Host-to-PCI Bridge Registers (Device 0)......................................................3-8
3.3.1
VID—Vendor Identification Register (Device 0).............................3-10
3.3.2
DID—Device Identification Register (Device 0) .............................3-10
3.3.3
PCICMD—PCI Command Register (Device 0)..............................3-11
3.3.4
PCISTS—PCI Status Register (Device 0) .....................................3-12
3.3.5
RID—Revision Identification Register (Device 0) ..........................3-13
3.3.6
SUBC—Sub-Class Code Register (Device 0) ...............................3-13
3.3.7
BCC—Base Class Code Register (Device 0) ................................3-13
3.3.8
MLT—Master Latency Timer Register (Device 0)..........................3-14
3.3.9
HDR—Header Type Register (Device 0).......................................3-14
3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14
3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15
3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16
3.3.13 CAPPTR—Capabilities Pointer Register (Device 0)......................3-16
3.3.14 NBXCFG—NBX Configuration Register (Device 0).......................3-16
3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19
3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20
3.3.17 PAM[6:0]—Programmable Attribute Map Registers
(Device 0)3-20
3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0)................3-22
3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24
3.3.20 MBSC—Memory Buffer Strength Control Register
(Device 0).......................................................................................3-25
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