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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 85/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
4-5
Functional Description
AGP accesses in this range are forwarded to PCI. When SMM is enabled the amount of memory
available to the system is equal to the amount of physical DRAM minus the value in the TSEG
register.
Note:
When extended SMRAM is used, the maximum amount of DRAM supported is limited to 256 MB.
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main DRAM to 4 GB (top of physical memory space supported
by the Intel
440ZX AGPset) is normally mapped to PCI. There are two exceptions to this rule:
Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT,
PMBASE, and PMLIMIT registers are mapped to AGP.
Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE
registers are mapped to the main DRAM.
There are two sub-ranges within the PCI Memory address range defined as APIC Configuration
Space and High BIOS Address Range. The AGP Memory Window and Graphics Aperture
Window
MUST NOT
overlap with these two ranges. These ranges are described in detail in the
following paragraphs.
APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h- FEEF_FFFFh)
This range is reserved for APIC configuration space. Note that the 82443ZX does not support the
I/O APIC and therefore does not support dual processors.
Note:
There is no provision to support an I/O APIC device on the 82443ZX or on AGP.
High BIOS Area (FFE0_0000h –FFFF_FFFFh)
The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS),
extended BIOS for PCI devices, and the A20 alias of the system BIOS. CPU begins execution from
the High BIOS after reset. This region is mapped to PCI so that the upper subset of this region
aliases to 16 MB–256 KB range
.
The actual address space required for the BIOS is less than 2 MB
but the minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered.
The PIIX4E supports a maximum of 1 MB in the High BIOS range.
4.1.1.3
AGP Memory Address Range
The 82443ZX can be programmed to direct memory accesses to the AGP bus interface when
addresses are within either of two ranges specified via registers in 82443ZX Device #1
configuration space. The first range is controlled via the Memory Base Register (MBASE) and
Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable
Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers
The 82443ZX positively decodes memory accesses to AGP memory address space as defined by
the following equations:
Memory_Base_Address
≤
Address
≤
Memory_Limit_Address
Prefetchable_Memory_Base_Address
≤
Address
≤
Prefetchable_Memory_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of memory claimed by the AGP compliant device. Normally, these ranges
reside above the Top-of-Main-DRAM and below High BIOS and APIC address ranges.
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