參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 91/116頁
文件大?。?/td> 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
4-11
Functional Description
NOTE:
1. For Memory cycles, REQa[4:3]# = ASZ#. The 82443ZX only supports ASZ# = 00 (32 bit address).
2. REQb[4:3]# = DSZ#. For the Pentium
II processor, DSZ# = 00 (64 bit data bus size).
3. LEN# = data transfer length as follows:
LEN#
Data length
00
≤
8 bytes (BE[7:0]# specify granularity)
01
Length = 16 bytes BE[7:0]# all active
10
Length = 32 bytes BE[7:0]# all active
11
Reserved
Table 4-5. Host Bus Transactions Supported By 82443ZX
Transaction
REQA[4:0]#
REQB[4:0]#
82443ZX Support
Deferred Reply
0 0 0 0 0
X X X X X
The 82443ZX initiates a deferred reply for a
previously deferred transaction.
Reserved
0 0 0 0 1
X X X X X
Reserved
Interrupt Acknowledge
0 1 0 0 0
0 0 0 0 0
Interrupt acknowledge cycles are forwarded to
the PCI bus.
Special Transactions
0 1 0 0 0
0 0 0 0 1
See separate table in Special Cycles section.
Reserved
0 1 0 0 0
0 0 0 1 x
Reserved
Reserved
0 1 0 0 0
0 0 1 x x
Reserved
Branch Trace Message
0 1 0 0 1
0 0 0 0 0
The 82443ZX terminates a branch trace
message without latching data.
Reserved
0 1 0 0 1
0 0 0 0 1
Reserved
Reserved
0 1 0 0 1
0 0 0 1 x
Reserved
Reserved
0 1 0 0 1
0 0 1 x x
Reserved
I/O Read
1 0 0 0 0
0 0 x LEN#
I/O read cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443ZX
configuration space are not forwarded to PCI.
I/O Write
1 0 0 0 1
0 0 x LEN#
I/O write cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443ZX
configuration space are not forwarded to PCI.
Reserved
1 1 0 0 x
0 0 x x x
Reserved
Memory Read &
Invalidate
0 0 0 1 0
0 0 x LEN#
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443ZX initiates an MRI cycle for a PCI/1
initiated write cycle to DRAM.
Reserved
0 0 0 1 1
0 0 x LEN#
Reserved
Memory Code Read
0 0 1 0 0
0 0 x LEN#
Memory code read cycles are forwarded to
DRAM or PCI/1.
Memory Data Read
0 0 1 1 0
0 0 x LEN#
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443ZX initiates a memory read cycle for a
PCI/1 initiated read cycle to DRAM.
Memory Write (no retry)
0 0 1 0 1
0 0 x LEN#
This memory write is a writeback cycle and
cannot be retried. The 82443ZX forwards the
write to DRAM.
Memory Write (can be
retried)
0 0 1 1 1
0 0 x LEN#
The normal memory write cycle is forwarded
to DRAM or PCI/1.
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