參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 51/116頁
文件大?。?/td> 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
3-27
Register Description
3.3.21
SMRAM—System Management RAM Control Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
72h
02h
Read/Write
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the
OPEN bit must be reset before the LOCK bit is set.
Bit
Description
7
Reserved
6
SMM Space Open (D_OPEN).
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made
visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When
D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only.
5
SMM Space Closed (D_CLS).
When D_CLS = 1 SMM space DRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space DRAM.
This will allow SMM software to reference "through" SMM space to update the display even when
SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are
not set at the same time.
4
SMM Space Locked (D_LCK).
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,
D_OPEN, H_SMRAM_EN, TSEG_SZ, TSEG_EN and DRB7 become read only. D_LCK can be
set to 1 via a normal configuration space write but can only be cleared by a power-on reset. The
combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the
future so that no application software (or BIOS itself) can violate the integrity of SMM space, even
if the program has knowledge of the D_OPEN function.
3
Global SMRAM Enable (G_SMRAME).
If G_SMRAME is set to a 1 and H_SMRAM_EN is set to
0, then Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the
A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function
this bit has be set to 1. Refer to the section on SMM for more details.
Once D_LCK is set, this bit becomes read only.
2:0
Compatible SMM Space Base Segment (C_BASE_SEG) (RO).
This field programs the location
of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are
right to access SMM space, otherwise the access is forwarded to PCI.
010 = Hardwired to 010 to indicate that the 82443ZX supports the SMM space at
A0000h–BFFFFh.
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