參數(shù)資料
型號(hào)： 82443ZX
廠商： INTEL CORP
元件分類(lèi)： 存儲(chǔ)控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁(yè)數(shù)： 77/116頁(yè)
文件大小： 533K
代理商： 82443ZX
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82443ZX Host Bridge Datasheet
3-53
Register Description
3.4.17
MBASE—Memory Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
20–21h
FFF0h
Read/Write
16 bits
This register controls the CPU to AGP non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
This register must be initialized by the configuration software.
3.4.18
MLIMIT—Memory Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
22–23h
0000h
Read/Write
16 bits
This register controls the CPU to AGP non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
This register must be initialized by the configuration software.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable AGP
address ranges (typically where control/status memory-mapped I/O data structures of the graphics
controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges
(typically graphics local memory). This segregation allows application of USWC space attribute to
be performed in a true plug-and-play manner to the prefetchable address range for improved CPU-
AGP memory access performance.
Note:
The configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent
overlap with each other and/or with the ranges covered with the main memory. There is no
provision in the 82443ZX hardware to enforce prevention of overlap and operations of the system
in the case of overlap are not guaranteed.
7
Fast Back-to-Back (FB2B1).
This bit is hardwired to 1. The 82443ZX as a target supports fast
back-to-back transactions on AGP.
6
Reserved.
5
66/60MHZ Capability.
Hardwired to 1.
4:0
Reserved.
Bit
Descriptions
Bit
Description
15: 4
Memory Address Base (MEM_BASE).
Corresponds to A[31:20] of the memory address.
Default=FFF0h
3:0
Reserved.
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