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參數(shù)資料
| 型號(hào)： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 60/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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Register Description
3-36
82443ZX Host Bridge Datasheet
3.3.31
ACAPID—AGP Capability Identifier Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A0–A3h
00100002h/00000000h
Read Only
32 bits
This register provides normal identifier for AGP capability.
3.3.32
AGPSTAT—AGP Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A4–A7h
1F000203h
Read Only
32 bits
This register reports AGP compliant device capability/status.
Bit
Description
31:24
Reserved
23:20
Major AGP Revision Number.
This field provides a major revision number of AGP specification
to which this version of the 82443ZX conforms. When the AGP DIS bit (PMCR[1]) is set to 0, this
number is set to value of “0001b” (i.e., implying Rev 1.x). When the AGP DIS bit (PMCR[1]) is set
to 1, This number is set to “0000b”.
19:16
Minor AGP Revision Number.
These bits provide a minor revision number of AGP specification
to which this version of 82443ZX conforms. This number is hardwired to value of “0000” (i.e.,
implying Rev x.0). Together with major revision number this field identifies 82443ZX as an AGP
REV 1.0 compliant device.
15:8
Next Capability Pointer.
AGP capability is the first and the last capability described via the
capability pointer mechanism.
0s = Hardwired to 0s to indicate the end of the capability linked list.
7:0
AGP Capability ID.
This field identifies the linked list item as containing AGP registers. When the
AGP DIS bit (PMCR[1]) is set to 0, this field has a value of 0000_0010b assigned by the PCI SIG.
When the AGP DIS bit (PMCR[1]) is set to 1, this field has a value of 00h.
Bit
Description
31:24
AGP Maximum Request Queue Depth (RO).
This field is hardwired to 1Fh to indicate a
maximum of 32 outstanding AGP command requests can be handled by the 82443ZX.
23:10
Reserved
9
AGP Side Band Addressing Supported.
This bit indicates that the 82443ZX supports side band
addressing. It is hardwired to 1.
8:2
Reserved
1:0
AGP Data Transfer Type Supported (R/W).
Bit 0 identifies if AGP compliant device supports 1x
data transfer mode and bit 1 identifies if AGP compliant device supports 2x data transfer mode.
Configuration software will update this field by setting only one bit that corresponds to the
capability of AGP master (after that capability has been verified by accessing the same functional
register within the AGP masters configuration space).
00 = Not allowed
01 = 1x data transfer mode supported
10 = 2x data transfer mode supported
11 = (default)
NOTE: The selected data transfer mode apply to both AD bus and SBA bus.
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