參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 66/116頁
文件大?。?/td> 533K
代理商： 82443ZX
Register Description
3-42
82443ZX Host Bridge Datasheet
3.3.39
DWTC—DRAM Write Thermal Throttling Control Register
(Device 0)
Offset:
Default:
Access:
Size:
E0h–E7h
0000_0000_0000_0000h
Read/Write/Lock
64 bits
A locking mechanism is included to protect contents of this register as well as the DRAM Read
Thermal Throttling Control register described below.
Bits
Description
63
Throttle Lock (TLOCK).
This bit secures the DRAM thermal throttling control registers.
1 = All configuration register bits in E0h–E7h and E8h–EFh (read throttle control) become read-
only.
0 = Default
62:46
Reserved
45:38
Global DRAM Write Sampling Window (GDWSW).
This 8-bit value is multiplied by 4 to define
the length of time in milliseconds (0–1020) over which the number of QWords written is counted.
37:26
Global QWord Threshold (GQT).
The 12-bit value held in this field is multiplied by 2^15 to arrive
at the number of QWords that must be written within the Global DRAM Write Sampling Window in
order to cause the thermal throttling mechanism to be invoked.
25:20
Throttle Time (TT).
This value provides a multiplier between 0 and 63 which specifies how long
thermal throttling remains in effect as a number of Global DRAM Write Sampling Windows. For
example, if GDWSW is programmed to 1000_0000b and TT is set to 01_0000b, then thermal
throttling will be performed for ~2 seconds once invoked (128 ms * 16).
19:13
Throttle Monitoring Window (TMW).
The value in this register is padded with four 0’s to specify
a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling
mechanism is invoked, DRAM writes are monitored during this window—if the number of
QWords written during the window reaches the Throttle QWord Maximum, then write requests
are blocked for the remainder of the window.
12:3
Throttle QWord Maximum (TQM).
The Throttle QWord Maximum defines the maximum number
of QWords between 0–1023 which are permitted to be written to DRAM within one Throttle
Monitoring Window while the thermal throttling mechanism is in effect.
2:0
DRAM Write Throttle Mode.
Normal DRAM write monitoring and thermal throttling operation are
enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved.
000-011 = Intel Reserved
100 = Normal Operations
101-111 = Intel Reserved
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