參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 92/116頁
文件大?。?/td> 533K
代理商： 82443ZX
Functional Description
4-12
82443ZX Host Bridge Datasheet
Table 4-6. Host Responses supported by the 82443ZX
RS2#
RS1#
RS0#
Description
82443ZX Support
0
0
0
idle
0
0
1
Retry Response
To avoid deadlock, this response is generated when a
resource cannot currently be accessed by the
processor. PCI-directed reads, writes, DRAM locked
reads, AGP reads and writes can be retried.
0
1
0
Deferred Response
This response can be returned for all transactions that
can be executed ‘out of order.’ PCI-directed reads
(memory, I/O and Interrupt Acknowledge) and writes
(I/O only), and AGP directed reads (memory and I/O)
and writes (I/O only) can be deferred.
0
1
1
Reserved
Reserved
1
0
0
Hard Failure
Not supported.
1
0
1
No Data Response
This is for transactions where the data has already
been transferred or for transactions where no data is
transferred. Writes and zero length reads receive this
response.
1
1
0
Implicit Writeback
This response is given for those transactions where
the initial transactions snoop hits on a modified cache
line.
1
1
1
Normal Data
Response
This response is for transactions where data
accompanies the response phase. Reads receive this
response.
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