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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 89/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
4-9
Functional Description
4.1.5
Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three
interfaces (i.e., Host bus, PCI or AGP).
4.1.5.1
PCI Interface Decode Rules
The 82443ZX accepts accesses from PCI to the following address ranges:
All memory read and write accesses to Main DRAM
Memory Write accesses to AGP memory range defined by MBASE, MLIMIT, PMBASE, and
PMLIMIT. 82443ZX will not respond to memory read accesses to this range.
Memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
PCI accesses that fall elsewhere within the PCI memory range will not be accepted. PCI cycles not
explicitly claimed by the 82443ZX are either subtractively decoded or master-aborted on PCI.
4.1.5.2
AGP Interface Decode Rules
Cycles Initiated Using PCI Protocol
Accesses between AGP and PCI are limited to memory writes using the PCI protocol. Write cycles
are forwarded to PCI if the addresses are not within main DRAM range, AGP memory ranges, or
Graphics Aperture range.
The 82443ZX will claim AGP initiated memory read transactions decoded to the main DRAM
range or the Graphics Aperture range. All other memory read requests will be master-aborted by
the AGP initiator as a consequence of 82443ZX not responding to a transaction.
If agent on AGP issues an I/O, PCI Configuration or PCI Special Cycle transaction, the 82443ZX
will not respond and cycle will result in a master-abort.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory (i.e., main DRAM address range or Graphics Aperture
range which is also physically mapped within DRAM but using different address range).
AGP-initiated cycles that target DRAM are not snooped on the host bus, even if they fall outside of
the AGP aperture range.
If cycle is outside of main memory range then it will terminate as follows:
Reads: return random value
Writes: dropped “on the floor” i.e. terminated internally without affecting any buffers or main
memory
ECC errors that occur on reads outside of DRAM are not reported or scrubbed.
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