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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 30/116頁 |
| 文件大小： | 533K |
| 代理商： | 82443ZX |
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Register Description
3-6
82443ZX Host Bridge Datasheet
3.2.3
PCI Bus Configuration Mechanism Overview
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space:
Configuration Read
and
Configuration Write
. Memory and I/O spaces are supported directly by the CPU.
Configuration space is supported by a mapping mechanism implemented within the chip-set. The
PCI specification defines two mechanisms to access configuration space, Mechanism #1 and
Mechanism #2. The 82443ZX supports only Mechanism #1.
The configuration access mechanism makes use of the CONFADD Register and CONFDATA
Register. To reference a configuration register a Dword I/O write cycle is used to place a value into
CONFADD that specifies the PCI bus, the device on that bus, the function within the device, and a
specific configuration register of the device function being accessed. CONFADD[31] must be 1 to
enable a configuration cycle. CONFDATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFADD. Any read or write to CONFDATA
will result in the Host Bridge translating CONFADD into a PCI configuration cycle.
3.2.3.1
Type 0 Access
If the Bus Number field of CONFADD is 0, a Type 0 Configuration cycle is performed on PCI (i.e.
bus #0). CONFADD[10:2] is mapped directly to AD[10:2]. The Device Number field of
CONFADD is decoded onto AD[31:11]. The Host-to-PCI Bridge entity within the 82443ZX is
accessed as Device #0 on the PCI bus segment. The Host- /AGP Bridge entity within the 82443ZX
is accessed as Device #1 on the PCI bus segment. To access Device #2, the 82443ZX will assert
AD13, for Device #3 will assert AD14, and so forth up to Device #20 for which will assert AD31.
Only one AD line is asserted at a time. All device numbers higher than 20 cause a type 0
configuration access with no IDSEL asserted, which will result in a Master Abort.
3.2.3.2
Type 1 Access
If the Bus Number field of CONFADD is non-zero, then a Type 1 Configuration cycle is performed
on PCI bus (i.e. bus #0). CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to
01 to indicate a Type 1 Configuration cycle. All other lines are driven to 0.
3.2.4
AGP Bus Configuration Mechanism Overview
This mechanism is compatible with PCI mechanism #1 supported for the PCI bus as defined above.
The configuration mechanism is the same for both accessing AGP or PCI-only devices attached to
the AGP interface.
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