參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 59/116頁
文件大?。?/td> 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
3-35
Register Description
3.3.30
ERRSTS—Error Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
91–92h
0000h
Read Only, Read/Write Clear
16 bits
This 16-bit register is used to report error conditions via the SERR# mechanism. SERR# is
generated on a zero to one transition of any of these flags (if enabled by the ERRCMD register).
Bit
Description
15:13
Reserved.
Read thermal Throttling Condition.
1 = Read thermal throttling condition occurred.
0 = Software writes “1” to clear this bit. Default=0
Write Thermal Throttling Condition.
1 = Write thermal throttling condition occurred.
0 = Software writes “1” to clear this bit. Default=0
AGP non-snoopable access outside of Graphics Aperture.
1 = AGP access occurred to the address that is outside of the graphics aperture range.
0 = Software writes “1” to clear this bit. Default=0
Invalid AGP non-snoopable DRAM read access (R/WC).
1 = AGP non-snoopable READ access was attempted outside of the graphics aperture and
outside of main memory (i.e,. in 640 KB – 1 MB range or above top of memory).
0 = Software must write a “1” to clear this status bit.
Access to Invalid Graphics Aperture Translation Table Entry (AIGATT) (R\WC).
1 = An invalid translation table entry was returned in response to a graphics aperture read or write
access.
0 = Software must write a “1” to clear this bit.
Not Applicable in the 82443ZX.
12
11
10
9
8
7:0
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