參數(shù)資料
型號(hào)： 82443ZX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 43/116頁
文件大?。?/td> 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
3-19
Register Description
3.3.15
DRAMC—DRAM Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
57h
00S0_0000b
Read/Write
8 bits
Bit
Description
7:6
Reserved.
5
Module Mode Configuration (MMCONFIG).
This bit is set by an external strapping option. The
combination of this bit and the SDRAMPWR bit (SDRAMC register) determine the functioning of
the CKE signals as defined as follows:
SDRAMPWR
MMCONFIG
CKE Operation
0
0
3 DIMM, CKE[5:0] driven, self-refresh entry staggered.
SDRAM dynamic power down available.
X
1
3 DIMM, CKE0 only, self-refresh entry not staggered. SDRAM
dynamic power down unavailable.
1
0
4 DIMM, GCKE only, self-refresh entry staggered. SDRAM
dynamic power down unavailable.
NOTE:
Under MMCONFIG mode, the AGP must be disabled.
4
Not Applicable in the 82443ZX.
3
DRAM Type (DT).
This field indicates the DRAM type used to populate the entire array. When
set to 0, EDO timings are used for all cycles to main memory. When set to 1, SDRAM timings
are used for all cycles to memory. EDO and SDRAM cannot be mixed within a system.
0 = EDO
1 = SDRAM
2:0
DRAM Refresh Rate (DRR).
The DRAM refresh rate is adjusted according to the frequency
selected by this field. Disabling the refresh cycle (000) results in the eventual loss of DRAM
data. Changing DRR value will reset the refresh request timer. This field is used in conjunction
with the SDRAM frequency bits in the NBXCFG register to determine the correct load value for
the refresh timer.
000 = Refresh Disabled
001 = 15.6 us
010 = 31.2 us
011 = 62.4 us
100 = 124.8 us
101 = 249.6 us
110 = Reserved
111 = Reserved
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
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