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參數(shù)資料
| 型號： | 82443ZX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 中文描述： | DRAM CONTROLLER, PBGA492 |
| 封裝： | BGA-492 |
| 文件頁數(shù)： | 95/116頁 |
| 文件大?。?/td> | 533K |
| 代理商： | 82443ZX |
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82443ZX Host Bridge Datasheet
4-15
Functional Description
The 82443ZX has multiple copies of some of the signals interfacing to memory. The interface
consists of the following pins.
Multiple copies
— CSA[3:0]#, CSB[3:0]#
— SRASA#
— SCASA#
— CKE[3:0] (for 2 DIMM configuration)
Single Copy
— MD[63:0]
— GCKE (for 4 DIMM configuration, however, the 82443ZX supports 2 DIMMs only.)
— FENA (FET switch control for 4 DIMM configuration, however, the 82443ZX supports 2
DIMMs only.)
The CS# pins function as RAS# pins in the case of EDO DRAMs. The DQM pins function as
CAS# pins in the case of EDO DRAMs. Two CS# lines are provided per row. These are
functionally equivalent. The extra copy is provided for loading reasons. Most pins utilize
programmable strength output buffers (refer to Register Section). When a row contains 16Mb
SDRAMs, MAA11 and MAB11 function as Bank Select lines. When a row contains 64Mb
SDRAMs, MAA/B[12:11] function as Bank Addresses (BA[1:0], or Bank Selects).
The entire memory array may be configured as either normal SDRAM, registered SDRAM or EDO
DRAM. Mixing DRAM types within one system is not supported. DIMMs may be populated in
any order. That is, any combination of rows may be populated.
Table 4-8 illustrates a sample of the possible DIMM socket configurations along with
corresponding DRB programming.
NOTE:
1. "S" denotes single-sided DIMM's, "D" denotes double-sided DIMM's.
4.3.1.1
Configuration Mechanism For DIMMS
Detection of the type of DRAM installed on the DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL, SDA
and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the 82443ZX for detecting the size and type of memory
installed. Type and size detection must be done via the serial presence detection pins.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the 82443ZX DRAM registers must
be initialized. The 82443ZX must be configured for operation with the installed memory types.
Detection of memory type and size is done via the System Management Bus (SMB) interface on
the PIIX4E. This two wire bus is used to extract the DRAM type and size information from the
serial presence detect port on the DRAM DIMMs.
Table 4-8. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations
DIMM0\
DIMM1
DRB0
DRB1
DRB2
DRB3
Total Memory
1MBx72/S
0
01h
01h
01h
01h
8 MB
2MBx72/S
0
02h
02h
02h
02h
16 MB
1Mx72/S
1Mx72/S
01h
01h
02h
02h
16 MB
0
4Mx72/S
00h
00h
04h
04h
32 MB
16Mx72/S
16Mx72/S
10h
10h
20h
20h
256 MB
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