參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 87/116頁
文件大小： 533K
代理商： 82443ZX
82443ZX Host Bridge Datasheet
4-7
Functional Description
NOTE:
1.
1 = Enabled and 0 = Disabled
Table 4-4 defines the control of the decode for all code fetches and data fetches to SMRAM ranges
(as defined by Table 4-3). The G_SMRAM bit provides a global disable for all SMRAM memory.
The D_OPEN bit allows software to write to the SMRAM ranges without being in SMM. BIOS
software can use this bit to initialize SMM code at Power up. The D_LCK bit limits the SMRAM
range access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be
forwarded to PCI. The SMM software can use this bit to write to video memory while running code
out of DRAM.
NOTE:
1.
1 = Enabled and 0 = Disabled
Refer to Section 4.8, “Power Management” on page 4-21 for more details on SMRAM support.
Reiteration:
Only un-cacheable SMM regions may overlap PCI or AGP Windows.
SMM regions will not overlap the AGP aperture.
Software (not in SMM) will not access PCI memory behind cacheable SMM regions.
PCI or AGP masters cannot access the SMM space.
Table 4-2. SMRAM Decoding
Name of Range
Transaction Address
DRAM Address
compatible (Range A)
A0000–BFFFFh
A0000–BFFFFh
HI-SMRAM (RANGE H)
256M + A0000h to 256M + FFFFFh
A0000–FFFFFh
TSEG (RANGE T)
256M + TOM to 256M + TOM - TSEG_SIZE
TOM to TOM - TSEG_SIZE
Table 4-3. SMRAM Range Decode
Global SMRAM
H_SMRAME
TSEG_EN
A Range
H Range
T Range
0
x
x
Disable
Disable
Disable
1
0
0
Enable
Disable
Disable
1
0
1
Enable
Disable
Enable
1
1
0
Disabled
Enable
Disable
1
1
1
Disabled
Enable
Enable
Table 4-4. SMRAM Decode Control
G_SMRAME
D_LCK
D_CLS
D_OPEN
SMM Mode
SMM Code
Fetch
SMM Data
Fetch
0
x
x
x
x
Disable
Disable
1
0
x
0
0
Disable
Disable
1
0
0
0
1
Enable
Enable
1
0
0
1
x
Enable
Enable
1
0
1
0
1
Enable
Disable
1
0
1
1
x
Invalid
Invalid
1
1
x
x
0
Disable
Disable
1
1
0
x
1
Enable
Enable
1
1
1
x
1
Enable
Disable
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