參數(shù)資料
型號： 82443ZX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： Intel㈢ 440ZX AGPset: Host Bridge/Controller
中文描述： DRAM CONTROLLER, PBGA492
封裝： BGA-492
文件頁數(shù)： 76/116頁
文件大?。?/td> 533K
代理商： 82443ZX
Register Description
3-52
82443ZX Host Bridge Datasheet
3.4.15
IOLIMIT—I/O Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
Read/Write
8 bits
This register controls the CPU to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
3.4.16
SSTS—Secondary PCI-to-PCI Status Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1E–1Fh
02A0h
Read Only, Read/Write Clear
16 bits
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e. AGP side) of the “virtual” PCI-to-PCI bridge embedded within 82443ZX.
Bit
Description
7:4
I/O Address Limit.
Corresponds to A[15:12] of the I/O address. Default=0
3:0
Reserved.
(Only 16 bit addressing supported.)
Bit
Descriptions
15
Detected Parity Error (DPE1).
Note that the PERRE1 bit does not affect the function of this bit.
Also the PERR# is not implemented in the 82443ZX.
1 = 82443ZX detected of a parity error in the address or data phase of AGP bus transactions.
0 = Software sets DPE1 to 0 by writing a 1 to this bit.
14
Received System Error (SSE1).
1 = 82443ZX asserted SERR# for any enabled error condition under device 1. Device 1 error
conditions are enabled in the SSTS and BCTRL registers.
0 = Software clears SSE1 to 0 by writing a 1 to this bit.
13
Received Master Abort Status (RMAS1).
1 = 82443ZX terminates a Host-to-AGP with an unexpected master abort.
0 = Software resets this bit to 0 by writing a 1 to it.
12
Received Target Abort Status (RTAS1).
1 = 82443ZX-initiated transaction on AGP is terminated with a target abort.
0 = Software resets RTAS1 to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS1).
STAS1 is hardwired to a 0, since the 82443ZX does not
generate target abort on AGP.
10:9
DEVSEL# Timing (DEVT1).
This 2-bit field indicates the timing of the DEVSEL# signal when the
82443ZX responds as a target on AGP, and is hard-wired to the value 01b (medium) to indicate
the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
01 = Medium. (hardwired)
8
Data Parity Detected (DPD1).
Hardwired to 0. 82443ZX does not implement G_PERR# function.
However, data parity errors are still detected and reported on SERR# (if enabled by SERRE,
SERRE1 and the BCTRL register, bit 0).
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