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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁數(shù)： | 87/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
A-9
Assuming a QSPI maximum data delay time (t
dd
.Q, SCK to MOSI) of 10 ns, to meet
MC145050 input data timing requirements, the minimum clock pulse width is the great-
er of t
wh
, t
wl
, or (t
dd
.Q + t
su
.A/D). This figure is 190 ns.
Data hold times on both the QSPI and the MC145050 are too minimal to present a
problem, since data is not allowed to change until one-half SCK period after the latch
is triggered. The minimum SCK period must be twice the largest minimum clock pulse
width since the QSPI generates a symmetrical SCK waveform. This number is 500 ns,
indicating a maximum SCK frequency of 2 MHz. The MC68332 will be clocked at a
system clock frequency of 16 MHz, allowing an SCK frequency of exactly 2 MHz. The
BAUD field value can be found from the following equation:
BAUD = system clock frequency / (2
desired SCK frequency)
Therefore, the BAUD field should be programmed to
BAUD = [16 MHz / (2
2 MHz)] = 4
Another parameter that must be determined is the minimum time that must elapse be-
tween asserting the MC145050 CS pin and providing the first SCK pulse. According to
Reference 4.
, the maximum propagation delay from CS to DOUT driven (t
PZL
, t
PZH)
is
2 A/D CLKs + 300 ns. Assuming a QSPI input data setup time of 10 ns and an A/D
CLK frequency of 2 MHz, the total delay must be at least 10 + 300 + (2
500) = 1.31
ms. A minimum setup time from CS to SCK (t
su)
is 2 A/D CLKs + 425 ns. Since this
value is 1.425 ms and is the larger value, the DSCKL field in QSPI SPCR1 must be
programmed to provide at least this amount of delay. The MC68332 User's Manual
(see
Reference 2.
) states the formula for DSCKL as follows:
delay time = DSCKL / system clock frequency
Solving for DSCKL gives
DSCKL = (1425 ns / 62.5 ns) = 22.8
Rounding up to the nearest whole delay, there are 23 DSCKL units for a total delay of
1.4375 ms. Also, the DSCK bit must be set in each command control byte that governs
a transfer to the MC145050; otherwise, the standard delay of one-half SCK period will
be used (in this case, 250 ns).
For a successful conversion to occur, a delay of 44 A/D CLKs must elapse from the
last falling edge of SCK to the next assertion of CS. The QSPI always provides a one-
half SCK delay after the last SCK edge before the CS pins change state. The delay
time before the next CS assertion must then be
(44
500 ns) - 250 ns = 21.75 ms
The equation for delay between transfers is
delay time = (32
DTL) / system clock frequency
thus, it follows that
F
Freescale Semiconductor, Inc.
n
.
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