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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊 |
| 文件頁數(shù)： | 55/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-27
meaningful data is to be sent out from the QSPI, the user should write the data to the
transmit data segment before enabling the QSPI.
If SPE is set and MSTR is not set, a low state on the slave select (PCS0/SS) pin com-
mences slave mode operation at the address indicated by NEWQP. The QSPI trans-
mits the data found in the transmit data segment at the address indicated by NEWQP,
and the QSPI stores received data in the receive data segment at the address indicat-
ed by NEWQP. Data is transferred in response to an external slave clock input at the
SCK pin.
Because the command control segment is not used, the command control bits and pe-
ripheral chip-select codes have no effect in slave mode operation. The QSPI does not
drive any of the four peripheral chip-selects as outputs. PCS0/SS is used as an input.
Although CONT cannot be used in slave mode, a provision is made to enable receipt
of more than 16 data bits. While keeping the QSPI selected (PCS0/SS is held low), the
QSPI stores the number of bits, designated by BITS, in the current receive data seg-
ment address, increments NEWQP, and continues storing the remaining bits (up to the
BITS value) in the next receive data segment address.
As long as PCS0/SS remains low, the QSPI continues to store the incoming bit stream
in sequential receive data segment addresses, until either the value in BITS is reached
or the end-of-queue address is used with wraparound mode disabled. When the end
of the queue is reached, the SPIF flag is asserted, optionally causing an interrupt. If
wraparound mode is disabled, any additional incoming bits are ignored. If wraparound
mode is enabled, storing continues at either address $0 or the address of NEWQP,
depending on the WRTO value.
When using this capability to receive a long incoming data stream, the proper delay
between transfers must be used. The QSPI requires time, approximately 1 μs at 16.78-
MHz system clock, to prefetch the next transmit RAM entry for the next transfer. There-
fore, the user may select a baud rate that provides at least a 1 μs delay between suc-
cessive transfers to ensure no loss of incoming data. If the system clock is operating
at a slower rate, the delay between transfers must be increased proportionately.
Because the BITSE option in the command control segment is no longer available,
BITS sets the number of bits to be transferred for all transfers in the queue until the
CPU changes the BITS value. As mentioned above, until PCS0/SS is negated
(brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS0/SS
is negated before the proper number of bits (according to BITS) is received, the QSPI,
the next time it is selected, resumes storing bits in the same receive data segment ad-
dress where it left off. If more than 16 bits are transferred before negating the PCS0/
SS, the QSPI stores the number of bits indicated by BITS in the current receive data
segment address, then increments the address and continues storing as described
above. Note that PCS0/SS does not necessarily have to be negated between trans-
fers.
Once the proper number of bits (designated by BITS) are transferred, the QSPI stores
the received data in the receive data segment, stores the internal working queue point-
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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